FIG. 1 is a wafer process cross section of a conventional Metal-Insulator-Metal (MIM) capacitor. In the example illustrated in FIG. 1, which is not to scale, above a substrate 10 there is an insulation or passivation layer 12, a bottom metal layer 14, dielectric layer 16, a top metal layer 18, an insulation layer 20, and a top passivation layer 22. The top metal layer 18, dielectric layer 16, and bottom metal layer 14 form the MIM capacitor C, which is graphically represented by the capacitor symbol. The insulation layer 12 electrically isolates the MIM capacitor C from the substrate 10, and the insulation layer 20 and passivation layer 22 electrically isolate the MIM capacitor C from structures above the MIM capacitor C. For clarity, the cross section illustrated in FIG. 1 shows only a portion of the MIM capacitor C; not shown in FIG. 1 are the electrical connections to the top metal layer 18 and bottom metal layer 14.
MIM capacitors that are connected to extrinsic pins, wire-bonding pads, or other external connections are susceptible to Electrostatic Discharge (ESD) damage, especially for Integrated Passive Components (IPCs) without intentionally fabricated active devices to form protection circuits. An ESD surge to top metal layer 18, for example, could cause a spark from the top metal layer 18 to the bottom metal layer 14, damaging the dielectric layer 16. This susceptibility can limit the ESD robustness of Monolithic Microwave Integrated Circuit (MMIC) chips, including those fabricated on a group III-V (“three-five”) type substrate, such as Gallium Arsenide (GaAs).
Conventional approaches to providing ESD protection involve the use of reversed-biased P-type semiconductor/N-type semiconductor (PN) junction diodes from the external connection to power and/or ground. However, creation of a PN junction diode involves an implantation step, e.g., to create one or two doped regions within the substrate, but a typical GaAs wafer process may not have an implant step, and thus using a conventional ESD protection method increases the cost of the wafer process by including at least one implant step, which requires additional masks, lithography, and/or etching steps. An alternative way to introduce PN junction diodes on GaAs for ESD protection is to grow p-type and n-type doped layers on the GaAs substrate. However, this method also shares the disadvantage of added cost introduced to the initial GaAs starting material.